1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a silicon oxide nitride oxide semiconductor (SONOS) type memory device including a high permittivity dielectric layer.
2. Description of the Related Art
A data storage capacity of a semiconductor memory device is proportional to the number of memory cells per unit area, i.e., an integration density. The semiconductor memory device includes many memory cells connected to one another.
In general, one memory cell of the semiconductor memory device, e.g., a dynamic random access memory (DRAM), includes a single transistor and a single capacitor. Accordingly, to increase the integration density of the semiconductor memory, the size of the transistor and/or the capacitor should be reduced.
As semiconductor technology and related electronic technologies are improved, a semiconductor memory device having a high integration density is required. However, reducing the size of the transistor and/or capacitor alone cannot satisfy this requirement.
The integration density of a semiconductor memory device is closely related to a design rule applied to the manufacturing process of the semiconductor memory. Accordingly, in order to increase the integration of the semiconductor memory device, a strict design rule must be used during manufacturing. This results in the photolithographic and etching processes having low process margins. In other words, more precise photolithographic and etching processes should be applied to the manufacturing of a highly integrated semiconductor memory device.
When the margins of the photolithographic and etching processes in the manufacturing process of the semiconductor memory device are decreased, yield also decreases. Therefore, a method of increasing the integration density of a semiconductor memory device while preventing the corresponding decrease in yield is needed.
Thus, a semiconductor memory device having a structure different from that of conventional semiconductor memory devices has been created in which the conventional capacitor has been replaced by other structures on the transistor. In these other structures, data are stored relying on different effects than that of a conventional capacitor. For example, these structures may rely on a giant magneto-resistance (GMR) effect or a tunneling magneto-resistance (TMR) effect. A silicon oxide nitride oxide semiconductor (SONOS) memory is such a semiconductor memory device. FIG. 1 illustrates a cross-sectional view of a conventional SONOS memory.
Referring to FIG. 1, the conventional SONOS memory includes a p-type semiconductor substrate 10, which will be referred to as a semiconductor substrate. A source region 12 and a drain region 14 doped with an n-type impurity are formed in the semiconductor substrate 10. A channel region 16 exists between the source and drain regions 12 and 14. A gate stack 30 is formed on the channel region 16 of the semiconductor substrate 10. The gate stack 30 includes a tunneling oxide layer 18, a silicon nitride (Si3N4) layer 20, a blocking oxide layer 22, and a gate electrode 24, which are sequentially stacked. The tunneling oxide layer 18 contacts the source and drain regions 12 and 14. The silicon nitride layer 20 includes a trap site having a predetermined density. Accordingly, when a predetermined voltage is applied to the gate electrode 24, electrons that have passed through the tunneling oxide layer 18 are trapped in the trap site of the silicon nitride layer 20. The blocking oxide layer 22 prevents the electrons from moving to the gate electrode 24 when the electrons are trapped in the trap site. The tunneling oxide layer 18 and the blocking oxide layer 22 may be formed of silicon oxide.
The threshold voltage of the conventional SONOS memory device when electrons are trapped in the trap site of the silicon nitride layer is different from the threshold voltage when electrons are not trapped. By using this characteristic, the conventional SONOS memory can store and reproduce data.
However, this conventional SONOS memory requires a long time to erase data stored therein and has a short retention time, i.e., it cannot retain stored data for a long time.
In addition, when a tunneling oxide layer and a blocking oxide layer are composed of silicon oxide, the SONOS memory needs a high driving voltage, e.g., about 10 V, thereby hindering high integration of the memory.